The invention relates generally to semiconductor device and integrated circuit fabrication and, in particular, to device structures and fabrication methods for a field-effect transistor.
Device structures for a field-effect transistor generally include a source region, a drain region, and a gate electrode configured to switch carrier flow in a channel formed in a body region. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, carrier flow occurs in the channel between the source and drain regions to produce a device output current. The body region of a planar field-effect transistor is located beneath the top surface of a substrate on which the gate electrode is supported.
A fin-type field-effect transistor (FinFET) is a non-planar device structure that may be more densely packed in an integrated circuit than planar field-effect transistors. A FinFET may include a fin consisting of a three-dimensional body of semiconductor material, heavily-doped source and drain regions formed in sections of the fin, and a gate electrode that wraps about the fin between the source and drain regions. The arrangement between the gate structure and fin body improves control over the channel and reduces the leakage current when the FinFET is in its ‘Off’ state in comparison with planar field-effect transistors. This, in turn, enables the use of lower threshold voltages than in planar field-effect transistors, and results in improved performance and lowered power consumption.